1. Field of the Invention
Embodiments relate to semiconductor memory devices. More particularly, embodiments relate to a semiconductor memory device and a data sensing method thereof.
2. Description of the Related Art
A unit cell of a dynamic random access memory (DRAM) is formed of one transistor and one capacitor. Due to their structural simplicity, DRAMs are widely used for semiconductor storage devices requiring a high integration density. However, due to charge leakage through the capacitor and transistor therein, the DRAM should be periodically refreshed for retaining its data.
In addition to a refresh operation, the DRAM may also perform writing and reading operations. The writing operation stores data in the unit cells and the reading operation retrieves data stored in the unit cells. It is well known that those operations are conducted using sense amplifiers.
The sense amplifiers operate in response to externally provided sensing control signals. The sensing control signals are generated by an edge driver included in a row decoder.
The DRAM also has a memory cell array to store all data up to a given design capacity. The row decoder is placed at one side of the memory cell array, which may cause a difference of signal propagation in transferring the sensing control signals to the sense amplifiers from the row decoder. For example, the sensing control signals arrive earlier at the sense amplifiers closer to the row decoder than to the sense amplifiers further from the row decoder. This effect is called ‘sensing skew’. It is desirable to reduce or eliminate such a sensing skew in the DRAM.